1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to an analog semiconductor device capable of preventing step between transistor and capacitor regions and a method of fabricating the same.
2. Description of the Related Art
In general, an analog semiconductor device stores information in various states, while a digital semiconductor device stores information in only two states, LOW and HIGH. The analog semiconductor device includes a resistor and capacitor at each node of its circuit. Since the resistance and capacitance vary with voltage, a resistor having a specific value is required.
FIG. 1 shows a cross-sectional view for describing a method of fabricating a conventional analog semiconductor device. Referring to FIG. 1, field oxide layers 2 are formed on a semiconductor substrate 1 by a well-known LOCOS(LOCal Oxidation of Silicon), to define a transistor region A and an analog capacitor region B. A gate insulating layer 3, a first doped polysilicon layer 4, a tungsten silicide layer 5 are then deposited on the overall substrate 21 in sequence and patterned, so that a gate 100a is formed on the substrate 21 of the transistor region A and a lower electrode 100b of a capacitor is formed on the field oxide layer 2 of the analog capacitor region B. On the lower electrode 100b, are then formed a polysilicon layer for buffer 6 and an oxide layer 7 acting as a dielectric layer. In case bonds between fluorine(F) gas of the tungsten silicide layer 5 and O.sub.2 gas are formed, the polysilicon layer for buffer 6 prevents capacitance decrease due to thickness variation of the oxide layer 7. Thereafter, an upper electrode 8 of the capacitor is formed on the oxide layer 7, thereby forming an analog capacitor 200. Here, the upper electrode 8 is formed to a second doped polysilicon layer. When patterning the gate 100a and the upper electrode 8, ARC layers 9 are formed on the tungsten silicide layer 5 and the second doped polysilicon layer, respectively.
However, as described above, since the analog capacitor 200 is formed on the field oxide layer 2, a step occurs between the transistor region A and capacitor region B. Owing to this step, the metal interconnection lines are opened when forming them and notching occurs when performing photolithography, thereby deteriorating reliability and yield of the device. Furthermore, these problems occur especially in devices under submicron.